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  rev 2 august 2005 1/13 13 STP10NK70Zfp STP10NK70Z n-channel 700v - 0.75 ? - 8.6a - to220-to220fp zener-protected supermesh? mosfet general features  extremely high dv/dt capability  improved esd capability  100% avalanche tested  gate charge minimized  very low intrinsic capacitances  very good manufacturing repeability description the supermesh? series is obtained through an extreme optimization of st?s well established strip-based powermesh? layout. in addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. applications  high current, high speed switching  ideal for off-line power supplies, adaptor and pfc order codes package internal schematic diagram type v dss r ds(on) i d pw STP10NK70Z STP10NK70Zfp 700 v 700 v <0.85 ? <0.85 ? 8.6 a 8.6 a 110 w 35 w 1 2 3 1 2 3 to-220 to-220fp sales type marking package packaging STP10NK70Z p10nk70z to-220 tube STP10NK70Zfp p10nk70zfp to-220fp tube www.st.com ( datasheet : )
1 electrical ratings STP10NK70Z - STP10NK70Zfp 2/13 1 electrical ratings table 1. absolute maximum ratings table 2. thermal data table 3. avalanche characteristics symbol parameter value unit to-220 to-220fp v ds drain-source voltage (v gs = 0) 700 v v dgr drain-gate voltage (r gs = 20k ? ) 700 v v gs gate-source voltage 30 v i d drain current (continuous) at t c = 25 c 8.6 8.6 ( note 3) a i d drain current (continuous) at t c = 100 c 5.4 5.4 ( note 3) a i dm note 2 drain current (pulsed) 34 34 ( note 3) a p tot total dissipation at t c = 25 c 150 35 w derating factor 1.20 0.28 w/ c vesd(g-s) g-s esd (hbm c=100pf, r=1.5k ?) 4000 v dv/dt note 1 peak diode recovery voltage slope 4.5 v/ns v iso insulation withstand volatge (dc) -- 2500 v t j t stg operating junction temperature storage temperature -55 to 150 c to-220 to-220fp unit rthj-case thermal resistance junction-case max 0.83 3.6 c/w rthj-amb thermal resistance junction-amb max 62.5 c/w t l maximum lead temperature for soldering purpose 300 c symbol parameter max value unit i ar avalanche current, repetitive or not-repetitive (pulse width limited by tj max) 8.6 a e as single pulse avalanche energy (starting tj=25 c, i d =i ar , v dd = 50v) 350 mj
STP10NK70Z - STP10NK70Zfp 2 electrical characteristics 3/13 2 electrical characteristics (t case = 25 c unless otherwise specified) table 4. on/off states table 5. dynamic table 6. switching times symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 1ma, v gs = 0 700 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating, v ds = max rating,tc = 125 c 1 50 a a i gss gate body leakage current (v ds = 0) v gs = 20v, v ds = 0 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 33.754.5 v r ds(on) static drain-source on resistance v gs = 10 v, i d = 4.5 a 0.75 0.85 ? symbol parameter test conditions min. typ. max. unit g fs note 4 forward transconductance v ds =15v, i d = 4.5a 7.7 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds =25v, f=1 mhz, v gs =0 2000 190 41 pf pf pf c oss eq. note 5 equivalent ouput capacitance v gs =0, v ds =0v to 560v 98 pf q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =560v, i d = 9 a v gs =10v (see figure 17) 64 12 33 90 nc nc nc symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd =350 v, i d =4.5 a, r g =4.7 ?, v gs =10v (see figure 18) 22 19 ns ns t d(off) t f turn-off delay time fall time v dd =350 v, i d =4.5a, r g =4.7 ?, v gs =10v (see figure 18) 46 19 ns ns t r(voff) t f t c off-voltage rise time fall time cross-over time v dd =560 v, i d =9a, r g =4.7 ?, v gs =10v (see figure 18) 11 10 22 ns ns ns
2 electrical characteristics STP10NK70Z - STP10NK70Zfp 4/13 table 7. source drain diode table 8. gate-source zener diode (1) i sd 8.6 a, di/dt 200a/s, v dd v (br)dss , t j t jmax (2) pulse width limited by safe operating area (3) limited only by maximum temperature allowed (4) pulsed: pulse duration = 300s, duty cycle 1.5% (5) c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80%v dss (6)the built-in back-to-back zener diodes have specifically been designed to enhance not only the device ? s esd capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. in this respect the zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device ? s integrity. these integrated zener diodes thus avoid the usage of external components. symbol parameter test conditions min. typ. max. unit i sd i sdm note 2 source-drain current source-drain current (pulsed) 8.6 34 a a v sd note 4 forward on voltage i sd =8.6 a, v gs =0 1.6 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd =9a, di/dt = 100a/s, v dd =35 v, tj=150 c 720 5.4 15 ns c a symbol parameter test conditions min. typ. max. unit bv gso note 6 gate-source breakdown voltage igs=1ma (open drain) 30 v
STP10NK70Z - STP10NK70Zfp 2 electrical characteristics 5/13 2.1 electrical characteristics (curves) figure 1. safe operating area for to-220 figure 2. thermal impedanc for to-220 figure 3. safe operating area for to-220fp figure 4. thermal impedance for to-220fp figure 5. output characteristics figure 6. transfer characteristics
2 electrical characteristics STP10NK70Z - STP10NK70Zfp 6/13 figure 7. transconductance figure 8. static drain-source on resistance figure 9. gate charge vs gate -source voltage figure 10. normalized gate threshold voltage vs temperatute figure 11. capacitance variations figure 12. normalized on resistance vs temperature
STP10NK70Z - STP10NK70Zfp 2 electrical characteristics 7/13 figure 13. source-drain diode forward characteristics figure 14. normalized bvdss vs temperature figure 15. maximum avalanche energy vs te mpera ture
3 test circuits STP10NK70Z - STP10NK70Zfp 8/13 3 test circuits figure 16. switching times test circuit for resistive load figure 17. gate charge test circuit figure 18. test circuit for indictive load switching and diode recovery times figure 19. unclamped inductive waveform figure 20. unclamped inductive load test circuit
STP10NK70Z - STP10NK70Zfp 4 package mechanical data 9/13 4 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com
4 package mechanical data STP10NK70Z - STP10NK70Zfp 10/13 dim. mm. inch min. typ max. min. typ. max. a 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 d 15.25 15.75 0.60 0.620 e 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 f 1.23 1.32 0.048 0.052 h1 6.20 6.60 0.244 0.256 j1 2.40 2.72 0.094 0.107 l 13 14 0.511 0.551 l1 3.50 3.93 0.137 0.154 l20 16.40 0.645 l30 28.90 1.137 ? p 3.75 3.85 0.147 0.151 q 2.65 2.95 0.104 0.116 to-220 mechanical data
STP10NK70Z - STP10NK70Zfp 4 package mechanical data 11/13 l2 a b d e h g l6 f l3 g1 123 f2 f1 l7 l4 l5 dim. mm. inch min. typ max. min. typ. max. a 4.4 4.6 0.173 0.181 b 2.5 2.7 0.098 0.106 d 2.5 2.75 0.098 0.108 e 0.45 0.7 0.017 0.027 f 0.75 1 0.030 0.039 f1 1.15 1.7 0.045 0.067 f2 1.15 1.7 0.045 0.067 g 4.95 5.2 0.195 0.204 g1 2.4 2.7 0.094 0.106 h 10 10.4 0.393 0.409 l2 16 0.630 l3 28.6 30.6 1.126 1.204 l4 9.8 10.6 .0385 0.417 l5 2.9 3.6 0.114 0.141 l6 15.9 16.4 0.626 0.645 l7 9 9.3 0.354 0.366 ? 3 3.2 0.118 0.126 to-220fp mechanical data
5 revision history STP10NK70Z - STP10NK70Zfp 12/13 5 revision history date revision changes 22-aug-2005 2 inserted ecopack indication
STP10NK70Z - STP10NK70Zfp 5 revision history 13/13 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com


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